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Link to End of chapter Exercises:. The previous Supplemental Chapter dealt with static parameters “DC characteristics” of voltage and current for digital chips.
This chapter on dynamic parameters extends our look at data sheets to what are called “AC characteristics”-various propagation delays and timing requirements. We also look at the relationship between power consumption and switching speed.
In the process it is necessary to compare various semiconductor versions of logic gates. The marketplace has provided an environment for a struggle between different versions of logic chips. Over the years some logic families have survived the struggle and thrived, while others have become virtually extinct. In this chapter we examine the surviving families, and study their evolution.
We see what virtues the survivors possess-chief among these are fast switching speed, low power consumption, high packing density and reasonable cost per gate. To proceed, you may want to review facts of electric circuits with energy-storing capacitors-including what an RC time constant is. After a central processing unit CPU upgrade in the RT could load the same benchmark program in 30 seconds.
Why the reduction in loading time? The hard disk hadn’t been changed, so the reduction must have come from improvements in the CPU. While there may have been some advances in the CPU’s “architecture”-notably more parallel processing and better direct memory access DMA -a major improvement was in the shorter propagation delays of individual gates and chips.
Faster hardware is better, all other things being equal. We’ll see in this chpt. Our first goal in this chapter will be to understand timing parameters in data sheets of chips. We want not so much to delve into the chip fabrication technology which brings about greater speed as to appreciate the limitations which timing parameters place on circuit design. When an output switches from one state to the other, propagation delay t-p is counted as the time from “instantaneous” input change to time of output reaching a new logic level, either VOL or VOH, as illustrated below.
Propagation delay of a gate is not the same thing as rise or fall time for an individual transistor. To propagate through an IC a signal may have to pass through several transistors and may pass through different transistor paths depending on the kind of input data, select, enable, etc being asserted. An npn bipolar transistor can turn on faster than it can turn off, which results in series chips having different propagation delays for LO-to-HI and HI-to-LO output transitions.
74L00 Datasheet, PDF – Alldatasheet
74l0 A small amount of delay in signal transmission is unavoidable because of the finite speed of light, which travels one foot per nanosecond signals move in wire at nearly the speed of light. But most delay in switching circuits is due to the time it takes charges stored in one place to move to another.
The removal of stored charge from a capacitor through a resistance to “ground” takes time, in the same way that emptying a bathtub through the drain takes time. Electronic switches are made of transistors. Consider the input side of a common-emitter transistor circuit, and the case of turning it off-charge caught in the base region must be removed before the flow of current from collector to emitter is stopped.
(PDF) 74L00 Datasheet download
To a certain approximation the base-emitter junction of a transistor acts like a capacitor. When a bipolar transistor-inverter is ON sufficient base current can “saturate” the device and fill its base region with electrons. The good news about saturation is that it lowers the collector-to-emitter voltage-which represents logical LOW-to about 0. The bad news is that a saturated bipolar transistor takes time to turn OFF. It takes extra time to remove charge from the thin base region.
The region can be modeled by a parasitic junction capacitance, shown in the figure below. The junction capacitance must be charged or discharged to or from 0.
When base current stops flowing the transistor will still allow IC to pass through the base, to the emitter, as electron “minority carriers” in npn so long as “majority” charge is stored in the base. In one case, the excess stored charge in the base will be removed by “recombination of minority and majority carriers,” a process which can take many nanoseconds. In another, the excess base charge may flow out through the resistor RB. Saturation can be prevented by placing a Schottky diode from base to collector: When the transistor is ON the Schottky diode diverts some of the RB current formally headed for the base, and “clamps” the base-to-collector voltage at about 0.
VCE is about 0. Another way to lower propagation delay-Decrease resistances around the chip-but if RB is reduced too much then IB will reach a dangerously high level and might burn out the transistor. How is propagation delay decreased in CMOS? By reducing the “channel length.
Propagation delay time is tP. Sometimes data sheets list only maximum values for each of these propagation delays, and in the case of the chip the values are tPLH for input to output 22 nsec, maximum tPHL for input to output 15 nsec Other variations for propagation delay in data sheets are minimum and typical. Usually a designer is worried about the worst-case time, which, for a combinational chip, is the maximum delay.
Sometimes a minimum delay is cause for concern, to prevent race conditions in flip flop circuits. For other chips, with several kinds of input, there can be more timing parameters. The 24 pin Texas Instruments “multiport video dynamic RAM” chip lists in its data sheets 73 timing parameters, mostly as minimum values, but in some cases as minimum and maximum.
The 73 timing parameters are explained with the help of 18 timing diagrams! Propagation delay can have meaning for more than a single chip. It can be measured or calculated for a hardware system with various data paths. The designer may have to search for minimum and maximum delays.
Maximum delay paths through digital systems are called critical paths. Examples of flip flop timing parameters are shown below for a clocked D flip flop with asynchronous SET. A single parameter that somewhat summarizes the performance of a clocked flip flop is fMAXthe maximum clock rate in Hertz the chip can handle before errors occur. Timing parameters for a 74 F 74 D flip flop are given below: Designers of electronic logic gates IC’s fight with the tendency of switching circuits to use more power the faster they switch.
Why the concern about power consumption? If the unit is not plugged in, batteries will drain more quickly the more power consumed per chip.
Because heat degrades the performance of an IC, and enough heat can burn it out, cooling systems must be installed where too much heat will be generated. Recall from mechanics that energy or work is force x distance. A 7 kg mass bowling ball slowly raised 0. An electron with a charge of Power is the rate of energy production or consumption.
Power can either be generated or consumed by a system. The power company and a “power supply” are aptly named, although a power supply normally transforms AC into DC, and is not a primary generator of electrical power, as the rotating machinery of a power plant is. As you may know, to compute power consumed in an electrical component, multiply voltage across the component times current flowing through. The diagram below shows the voltage and current conventions for positive power absorbed by a resistor: Below the formula for power in terms of current and voltage is developed.
We include a time parameter in the power formula as a reminder that power can be an instantaneous quality. Data sheets for a chip list ICCsupply current for a chip with the understanding of no load on the output pins. Connect the ammeter between the power supply and the chip to monitor ICC. How many chips would it take to [change a light bulb?
The time-varying voltage from the power company is converted to steady “DC” voltage in a power supply. When a power supply delivers power to its output ports it is an active device or system; a passive device, like a resistor, absorbs power. The figure below shows conventions for Integrated circuit chips are power-absorbing devices. A passive device which absorbs power gets warm. A light bulb absorbs power from the power company and radiates a little light and a lot of heat.
Some chips, particularly display drivers like themay get hot to the touch because they’re consuming a lot of power for their small size, sending current out to display segments-an “8” signal should feel hotter than a “1. For CMOS gates dynamic power dissipation is the main form of power dissipation; power consumed by a CMOS chip is almost linear with frequency of switching.
Multiply [power x time] and units of energy result.
Multiply the delay time per state switch and power consumed by chip, and you have energy used per state switch. If you inspect data sheets of chips from different logic families, you’ll find that switching speed increase is generally accompanied by an increase in current delivered to the chip.
The generation of heat would not be a matter of concern to us were it not for the fact that semiconductor switches can be datssheet by dataaheet temperatures.
Why does heat damage chips?
7400 / 74xxx TTL Series ICs
In commercial IC devices, however, aluminum is used as a metallization layer for routing of wire-like connections. There’s not really much disruption of the semiconductor crystal structure from excess heat in chips. Electrostatic-not heat- damage to CMOS can cause a filament of metal to blast through a junction, and thereby produce a local short circuit.
Catastrophic failure from heat is not the only concern. Higher temperatures can cause chips to operate at slower speeds. Sand to Circuit,” a 40 min. VHS color video datasheef In some cases, such as processing radar or video in real time, the fastest chips datashee must be used, and the costs in power consumed, heat generated and circuits artificially cooled must be paid.
Think of the heat generated by the muscles of the animals below. In a narrow sense a logic family is a set of small and medium-scale integrated circuits, fabricated from a common process, which span the range of gates and flip flops that a logic designer may find useful in assembling a large digital system.
Datashheet two digital logic technologies are in the super-family category: TTL was not the first logic family, but by the late 60’s chips in the series had a combination of shorter propagation delay and lower power consumption, compared to the now obsolete families of diode logic, resistor-transistor logic, and diode-transistor logic.
CMOS started out in the ‘s as the series family, but its virtue of low static power consumption, and breakthroughs in speed thanks to narrow channel fabrication, have allowed CMOS to become the technology of choice for highly integrated circuits.